High Speed Low Power Voltage Comparator in 0.18μm CMOS Process for Flash ADCs

In this paper a novel low power comparator in a standard 0.18 mu m CMOS process has been proposed which is capable of resolving 1mV voltage difference between its input nodes. Employing the dynamic latch structure for the implementation of the circuitry, the designed circuit can operate for the clock frequencies up to 400MHz. To avoid the body effect of MOS transistors for utilized MOSIS technology, the input preamplifier stage has been proposed by PMOS differential pair transistors which considerably enhance the speed performance of the designed architecture. Because of such excellent speed behavior, this work can be a good choice for high speed Flash ADCs. Post-layout simulation results confirm the correct behavior of the proposed structure while the power consumption is 130 mu W for the clock frequency of 1MHz from a 1.8V power supply.