A folded floating-gate differential pair for low-voltage applications

I present a new folded differential pair topology that is suitable for low-voltage applications. The new differential pair is made from floating-gate MOS (FGMOS) transistors and simultaneously provides a rail-to-rail common-mode input voltage range a high rejection of the common-mode input voltage by keeping the sum of the two output currents fixed. Moreover, when biased in weak or moderate inversion, the allowable output voltage swing is also almost from rail-to-rail. I discuss the operation of the circuit and some of the trade-offs involved in its design. I also show experimental measurements from a version of the circuit, operating on a single 1.8-V power supply, that was breadboarded from transistors fabricated in a 1.2-mu m double-poly n-well CMOS process.