A low-impedance, sub-bandgap 0.6 μm CMOS reference with 0.84% trimless 3-σ accuracy and 230 dB worst-case PSRR up to 50 MHz

Modern mobile applications demand high performance from low supply voltages to reduce power (extend battery life) and survive low breakdown voltages (imposed by sub-micron CMOS technologies), which is why precise low-impedance sub-bandgap references (below 1.2 V) that are independent of process, package stress, supply, load, and temperature are critical. However, improving dc accuracy by trimming requires test time (cost) in production and dynamic-element matching (DEM) introduces switching noise. Additionally, improving ac accuracy by rejecting supply ripple with cascodes increases headroom requirements and shunting coupled noise with series low-impedance buffers introduces temperature-sensitive offsets that degrade dc accuracy. This paper presents a prototyped 0-5 mA, 890 mV, low-impedance, 0.6 mu m CMOS reference with a trimless 3-sigma unloaded dc accuracy of 0.84% across -40 and 125 degrees C (2.74% when loaded with 0-5 mA and supplied from 1.8 to 3 V) and a worst-case power-supply ripple rejection (PSRR) of -30 dB up to 50 MHz. The design adopts a low-cost, noise-free, self-selecting Survivor scheme to automatically select the best matching pair of devices among a bank of similar pairs during start-up (or power-on reset) and use them for critical functions in the circuit. A compact, low-voltage, charge-pumped cascoding strategy and a bandgap-embedded shunt-feedback loop suppress supply and coupled noise.