A 1mW 4b 1GS/s Delay-Line based Analog-to-Digital Converter

被引：8
|
作者：
Tousi, Yahya M. [1 ]
Li, Guansheng [1 ]
Hassibi, Arjang [2 ]
Afshari, Ehsan [1 ]
机构：
[1] Cornell Univ, Sch Elect & Comp Engn, Ithaca, NY 14853 USA
[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
来源：
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年
关键词：
CMOS; ADC;
D O I：
10.1109/ISCAS.2009.5117957
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.
引用
收藏
页码：1121 / +
页数：2
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