Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs

被引：7

作者：

Frank, DJ ^{[1
]}

Wong, HSP ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Heights, NY 10598 USA

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2000年 / 28卷 / 5-6期

关键词：

high-k dielectric; MOSFET; scaling; double-gate MOSFET;

D O I：

10.1006/spmi.2000.0952

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

We present an analysis of the scaling behavior of MOSFETs with high-k gate insulators which elucidates the useful design space for such insulators. This analysis demonstrates that the design space is smaller than might be hoped and that within it, nanoscale bulk MOSFETs can only gain up to similar to 20% additional scaling by use of high-k insulators, while symmetric double-gated FETs may gain up to similar to 30%. It is shown that this analysis does not depend significantly on the Sate sidewall dielectric constant or its spacing. (C) 2000 Academic Press.

引用

页码：485 / 491

页数：7

共 5 条

[1]

BUTURLA E, 1989, NASCODE, V6, P291

[2] Generalized scale length for two-dimensional effects in MOSFET's [J].

Frank, DJ ;

Taur, Y ;

Wong, HSP .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (10) :385-387

[3] Breakdown measurements of ultra-thin SiO2 at low voltage [J].

Stathis, JH ;

Vayshenker, A ;

Varekamp, PR ;

Wu, EY ;

Montrose, C ;

McKenna, J ;

DiMaria, DJ ;

Han, LK ;

Cartier, E ;

Wachnik, RA ;

Linder, BP .

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, :94-95

[4] CMOS scaling into the nanometer regime [J].

Taur, Y ;

Buchanan, DA ;

Chen, W ;

Frank, DJ ;

Ismail, KE ;

Lo, SH ;

SaiHalasz, GA ;

Viswanathan, RG ;

Wann, HJC ;

Wind, SJ ;

Wong, HS .

PROCEEDINGS OF THE IEEE, 1997, 85 (04) :486-504

[5] Fringing-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-K gate dielectrics [J].

Yeap, GCF ;

Krishnan, S ;

Lin, MR .

ELECTRONICS LETTERS, 1998, 34 (11) :1150-1152

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