Gated-Vdd:: A circuit technique to reduce leakage in deep-submicron cache memories

被引:313
作者
Powell, M [1 ]
Yang, SH [1 ]
Falsafi, B [1 ]
Roy, K [1 ]
Vijaykumar, TN [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
来源
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2000年
关键词
D O I
10.1109/LPE.2000.876763
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications, This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V-dd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V-dd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact an performance.
引用
收藏
页码:90 / 95
页数:6
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