Interpolating time counter with 100 ps resolution on a single FPGA device

被引：97

作者：

Szplet, R ^{[1
]}

Kalisz, J ^{[1
]}

Szymanowski, R ^{[1
]}

机构：

[1] Mil Univ Technol, PL-00908 Warsaw 49, Poland

来源：

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT | 2000年 / 49卷 / 04期

关键词：

delay circuits; field programmble gate arrays; time counters; time domain measurements; time-to-digital converters;

D O I：

10.1109/19.863942

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the logic and performance of an interpolating time counter integrated on a single Field-Programmable Gate Array (FPGA) device. The resolution of 100 ps (LSB) was obtained because of the new design of the FPCA delay lines used for precise time-to digital conversion, acid the use of enhanced CMOS FPGA technology. The worst-case random error of 170 ps has been lowered to 70 ps by software correction of the nonlinearity of the delay lines. The counter can measure time Intervals from 0-43 s and frequency up to 200 MHz. The maximum power consumption of the counter chip is 260 mW.

引用

页码：879 / 883

页数：5

共 14 条

[1] An integrated high resolution CMOS timing generator based on an array of delay locked loops [J].