ProPRAM: Exploiting the Transparent Logic Resources in Non-Volatile Memory for Near Data Computing

被引:9
作者
Wang, Ying [1 ]
Han, Yinhe [1 ]
Zhang, Lei [1 ]
Li, Huawei [1 ]
Li, Xiaowei [1 ]
机构
[1] Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing, Peoples R China
来源
2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2015年
关键词
D O I
10.1145/2744769.2744897
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Emerging highly-parallel and big data applications have renewed the research interest in Processing-in-Memory (PIM) architectures. However, moving powerful processing unit into the CMOS-incompatible DRAM chips is not cost-effective for large capacity memory. In this work, we observe that Non-Volatile Memory is often naturally incorporated with basic logics like Data Comparison Write or Flip-n-Write modules that are essential for cell SET/REST operation. In contrast to other conventional PIM or Near Data Computing (NDC) architectures, ProPRAM, as a typical Active NVM, abandons the design approach of moving accelerators or customized processors into memory devices, but begins with exploiting the existing resources inside the memory chips to accelerate the key non-compute-intensive functions for emerging big data applications. With slight hardware and architectural modification, we succeed to expose the transparent peripheral logics to the application layer through instruction set extension and exploit them for in-field bulk data processing with limited hardware cost. Compared to conventional CPU-centric systems, ProPRAM achieves an excellent optimization on energy-efficiency (15x) for important data-intensive micro-benchmarks and kernels.
引用
收藏
页数:6
相关论文
共 24 条
  • [1] Ahmad F., TECHNICAL REPORT
  • [2] [Anonymous], 2013, Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA '13, DOI [10.1145/2508148.2485939, DOI 10.1145/2485922.2485939, 10.1145/2485922.2485939]
  • [3] BEDESCHI F, 2009, J SOLID STATE CIRC, V44, P217, DOI DOI 10.1109/JSSC.2008.2006439
  • [4] Chhugani J, 2008, PROC VLDB ENDOW, V1, P1313
  • [5] Chung Hoeju, 2011, P SOL STAT CIRC C IS, P588
  • [6] Dae Hyun Kim, 2012, 2012 IEEE International Solid-State Circuits Conference (ISSCC), P188, DOI 10.1109/ISSCC.2012.6176969
  • [7] NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
    Dong, Xiangyu
    Xu, Cong
    Xie, Yuan
    Jouppi, Norman P.
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (07) : 994 - 1007
  • [8] Gebis J., 2004, DESIGN AUTOMATION ST
  • [9] PROCESSING IN MEMORY - THE TERASYS MASSIVELY-PARALLEL PIM ARRAY
    GOKHALE, M
    HOLMES, B
    IOBST, K
    [J]. COMPUTER, 1995, 28 (04) : 23 - 31
  • [10] Graefe G., 2001, P INT C DAT ENG ICDE