Novel self-aligned Ti silicide process for scaled CMOS technologies with low sheet resistance at 0.06-μm gate lengths

被引：9

作者：

Kittl, JA ^{[1
]}

Hong, QZ ^{[1
]}

Rodder, M ^{[1
]}

Breedijk, T ^{[1
]}

机构：

[1] Texas Instruments Inc, Semicond Proc & Device Ctr, Dallas, TX 75265 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 1998年 / 19卷 / 05期

关键词：

CMOS; Molybdenum; preamorphization; silicide; titanium;

D O I：

10.1109/55.669732

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel Ti self-aligned silicide (salicide) process using a combination of low dose Molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-mu m gate lengths (Mean = 5.2 Omega/sq, Max = 5.7 Omega/sq at 0.07 mu m; Mean = 6.7 Omega/sq, Max = 8.1 Omega/sq at 0.06 mu m, TiSi2 thickness on S/D = 38 nm), in contrast with previous Ti salicide processes which failed below 0.10 mu m. The process was successfully implemented into a 1.5 V, 0.12-mu m CMOS technology achieving excellent drive currents (723 and 312 mu A/mu m at I-OFF = 1 nA/mu m for nMOS and pMOS, respectively).

引用

页码：151 / 153

页数：3

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