Improving circuit performance with multispeculative additive trees in high-level synthesis

被引:6
作者
Del Barrio, Alberto A. [1 ]
Hermida, Roman [1 ]
Memik, Seda Ogrenci [2 ]
Mendias, Jose M. [1 ]
Molina, Maria C. [1 ]
机构
[1] Univ Complutense Madrid, Fac Informat, E-28040 Madrid, Spain
[2] Northwestern Univ, Dept Elect Engn & Comp Sci, Evanston, IL 60208 USA
关键词
Variable-latency functional units; Speculation; Additive operation trees; High-level synthesis; UNITS;
D O I
10.1016/j.mejo.2014.06.005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of High-Level Synthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs. (C) 2014 Elsevier Ltd. All rights reserved
引用
收藏
页码:1470 / 1479
页数:10
相关论文
共 28 条
[1]   Compaction-based concurrent error detection for digital circuits [J].
Almukhaizim, S ;
Drineas, P ;
Makris, Y .
MICROELECTRONICS JOURNAL, 2005, 36 (09) :856-862
[2]  
[Anonymous], 2018, Computer Arithmetic Algorithms
[3]  
[Anonymous], 2008, HIGH LEVEL SYNTHESIS
[4]  
BANERES D, 2009, VARIABLE LATENCY DES, P1704
[5]   Telescopic units: A new paradigm for performance optimization of VLSI designs [J].
Benini, L ;
Macii, E ;
Poncino, M ;
De Micheli, G .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (03) :220-232
[6]  
Brooks D., 1999, DYNAMICALLY EXPLOITI, P13
[7]  
Burden RL, 2000, Numerical analysis, V7th
[8]   Pipelined adders [J].
Dadda, L ;
Piuri, V .
IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (03) :348-356
[9]  
De Micheli G., 1994, SYNTHESIS OPTIMIZATI
[10]  
Del Barrio A.A., 2013, MULTISPECULATIVE ADD, P188