Processing-in-Memory Technology for Machine Learning: From Basic to ASIC

被引：8

作者：

Taylor, Brady ^{[1
]}

Zheng, Qilin ^{[1
]}

Li, Ziru ^{[1
]}

Li, Shiyu ^{[1
]}

Chen, Yiran ^{[1
]}

机构：

[1] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27707 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2022年 / 69卷 / 06期

关键词：

Processing-in-memory; machine learning accelerator; analogcomputation; dataflow optimization; UNIT-MACRO; COMPUTATION; SRAM; ACCELERATOR;

D O I：

10.1109/TCSII.2022.3168404

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Due to the need for computing models that can process large quantities of data efficiently and with high throughput in many state-of-the-art machine learning algorithms, the processing-in-memory (PIM) paradigm is emerging as a potential replacement for standard digital architectures on these workloads. In this tutorial, we review the progress of PIM technology in recent years, at both the circuit and architecture level. We further present an analysis of when and how PIM technology surpasses the performance of conventional architectures. Finally, we outline our vision for the future of PIM technology.

引用

页码：2598 / 2603

页数：6

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