Wafer level interconnects for 3D packaging

被引：0
|
作者：
Banerjee, SR [1 ]
Drayton, RF [1 ]
机构：
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
来源：
54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/ECTC.2004.1320315
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.
引用
收藏
页码：1513 / 1518
页数：6
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