共 26 条
[2]
A fast and accurate approach for full chip leakage analysis of nano-scale circuits considering intra-die correlations
[J].
20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA,
2007,
:589-+
[3]
Bishop C. M, 2007, NEURAL NETWORKS PATT
[5]
Borkar S, 2003, DES AUT CON, P338
[7]
Full-chip analysis of leakage power under process variations, including spatial correlations
[J].
42ND DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2005,
2005,
:523-528
[10]
Horowitz M, 2005, INT EL DEVICES MEET, P11