Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology

被引:68
作者
Yamaoka, M [1 ]
Osada, K [1 ]
Tsuchiya, R [1 ]
Horiuchi, M [1 ]
Kimura, S [1 ]
Kawahara, T [1 ]
机构
[1] Hitachi Ltd, Cent Res Lab, Kokubunji, Tokyo 1858601, Japan
来源
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年
关键词
D O I
10.1109/VLSIC.2004.1346590
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We have developed the new "Yin-Yang" feedback technology for SRAM cells. This technology is applied to sixtransistor cells and four-transistor cells, which are composed of transistors with the new D2G-SOI structure. At the 65nm process node, these cells can operate at 0.7 V in massproduced LSIs under real usage conditions. Max. operating speeds are 300 MHz for the six-transistor and 200 MHz for the four-transistor cell. Leakage current of the four-transistor cell is about 1/1000 that of a conventional four-transistor cell. These cells provide a SRAM menu that allows us to optimally balance the requirements of various types of SRAM in low-power LSIs.
引用
收藏
页码:288 / 291
页数:4
相关论文
共 5 条
[1]  
Mizuno H, 1995, 1995 SYMPOSIUM ON VLSI CIRCUITS, P25, DOI 10.1109/VLSIC.1995.520671
[2]   A 1.9-μm2 loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology [J].
Noda, K ;
Matsui, K ;
Imai, K ;
Inoue, K ;
Tokashiki, K ;
Kawamoto, H ;
Yoshida, K ;
Takeda, K ;
Nakamura, N ;
Kimura, T ;
Toyoshima, H ;
Koishikawa, Y ;
Maruyama, S ;
Saitoh, T ;
Tanigawa, T .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :643-646
[3]  
Osada K., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P168, DOI 10.1109/ISSCC.2001.912589
[4]  
SEEVINCK E, 1987, IEEE JSSCC SC, V22
[5]   0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array-voltage scheme [J].
Yamaoka, M ;
Osada, K ;
Ishibashi, K .
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2002, :170-173