A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC

被引：24

作者：

Kim, Shinwoong ^{[1
]}

Hong, Seunghwan ^{[1
]}

Chang, Kapseok ^{[2
]}

Ju, Hyungsik ^{[2
]}

Shin, Jaewook ^{[2
]}

Kim, Byungsub ^{[1
]}

Park, Hong-June ^{[1
]}

Sim, Jae-Yoon ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol POSTECH, Pohang 37673, South Korea

[2] ETRI, Daejeon 34129, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2016年 / 51卷 / 02期

关键词：

All-digital; frequency synthesizer; fractional-N; phase-locked loop; standard cell; synthesis; time-to-digital converter (TDC); PHASE-LOCKED LOOP; FREQUENCY-SYNTHESIZER; COARSE;

D O I：

10.1109/JSSC.2015.2494365

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm(2) and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.

引用

页码：391 / 400

页数：10

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