Cell-Aware Test

被引：132

作者：

Hapke, Friedrich ^{[1
]}

Redemund, Wilfried ^{[1
]}

Glowatz, Andreas ^{[1
]}

Rajski, Janusz ^{[2
]}

Reese, Michael ^{[3
]}

Hustava, Marek ^{[4
]}

Keim, Martin ^{[2
]}

Schloeffel, Juergen ^{[1
]}

Fast, Anja ^{[1
]}

机构：

[1] Mentor Graph Dev Deutschland GmbH, D-21079 Hamburg, Germany

[2] Mentor Graph Corp, Wilsonville, OR 97070 USA

[3] AMD Inc, Austin, TX 78735 USA

[4] ON Semicond, Brno 61900, Czech Republic

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2014年 / 33卷 / 09期

关键词：

Automatic test pattern generation; cell-aware test; defect-based test; defective parts; design for testability; failure analysis; FinFET test; logic testing; test data compression; transistor-level test;

D O I：

10.1109/TCAD.2014.2323216

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

引用

页码：1396 / 1409

页数：14

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