DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets

被引：2

作者：

Cretu, B. ^{[1
]}

Veloso, A. ^{[2
]}

Simoen, E. ^{[2
,3
]}

机构：

[1] Normandie Univ, UNICAEN, ENSICAEN, CNRS,GREYC, F-14000 Caen, France

[2] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[3] Univ Ghent, Solid State Phys Dept, B-9000 Ghent, Belgium

来源：

SOLID-STATE ELECTRONICS | 2022年 / 194卷

关键词：

ELECTRICAL NOISE; 1/F NOISE; EXTRACTION; MOSFETS;

D O I：

10.1016/j.sse.2022.108360

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

DC and low frequency noise measurements are performed in p-channel gate all around (GAA) vertically stacked silicon nanosheets (NS) at room temperature. The key DC parameters such as threshold voltage, low field mobility, access resistance and subthreshold swing are estimated. Preliminary low frequency noise studies reveal that the 1/f noise may be explained in weak to moderate inversion by the carrier number fluctuation mechanism, while in strong inversion the access resistance noise prevails.

引用

页数：4

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