Scan latch design for delay test

被引：16

作者：

Savir, J ^{[1
]}

机构：

[1] New Jersey Inst Technol, ECE Dept, Newark, NJ 07102 USA

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

LSSD; SRL; BIST; LFSR; MISR; delay test;

D O I：

10.1109/TEST.1997.639650

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips.

引用

页码：446 / 453

页数：8