Printed-Circuit Board (PCB) Charge Induced Product Yield-Loss During The Final Test

被引：0

作者：

Lee, Jian-Hsing ^{[1
]}

Takahashi, Kunihiko ^{[2
]}

Prabhu, Manjunatha ^{[1
]}

Natarajan, Mahadeva Iyer ^{[1
]}

机构：

[1] GLOBALFOUNDRIES Inc, 400 Stonebreak Rd Ext, Malta, NY 12020 USA

[2] GLOBALFOUNDRIES Inc, Singapore 738406, Singapore

来源：

2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2015年

关键词：

resistor; Electrostatic Discharge (ESD); Printed Circuit Board (PCB);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that the voltage is high enough to damage the components of the low voltage circuits (1.8V), but is still too low to turn on the ESD protection device.

引用

页数：5