A Power and Area Efficient Architecture of Convolver Based on Ram

被引：1

作者：

Chen, Chen ^{[1
]}

Chen, Yun ^{[1
]}

Chen, Yuan ^{[1
]}

Pan, An ^{[1
]}

Zeng, Xiao-Yang ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab AS1C & Syst, Shanghai 201203, Peoples R China

来源：

2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

Convolver; correlator; ram; register; power; area;

D O I：

10.1109/ASICON.2009.5351564

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a novel architecture of the convolver which can also be used as a correlator (depend on the order in which the input sequence are put in). It is power and area efficient compared with the typical architectures based on registers. Two groups of convolver are implemented to show the improvement. One group deals with two 12bit data sequences of length 64, while another deals with two 12bit data sequences of length 256, with each group containing a ram based one and a conventional one. The synthesis results by DC using SMIC 0.13um library and the results of Prime Power shows that in the second group, the area and power of the ram based one can be reduced to 91% and only 77% of the conventional one, respectively.(1)

引用

页码：835 / 838

页数：4

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