Optimizing Redundancy Design for Chip-Multiprocessors for Flexible Utility Functions

Yield of chip-multiprocessors (CMP) can be improved by adding spares to the design. The optimal spare configuration has previously been derived for certain evaluation metrics, such as yield per area, performance-averaged yield, and so on. However, all previous approaches are limited to the scenario where only those chips which have the full-configuration (i.e., have n working processors, where n is the number of processors in the CMP's specifications) can be sold. In the meantime, yield problems have forced vendors of high-volume CMPs to sell chips with different numbers of working processors. The purpose of this paper is to extend our recent framework for the optimal redundancy design to systematically capture such flexibilities. We first define utility function for CMPs in terms of two functions: (i) the number-of-processors-binning (NPB) function, which captures the range of the number of (enabled) working processors over which a chip can be sold, and (ii) the value function, which captures how the value of a chip to the user depends upon the number of processors enabled in the chip. We use case studies to identify the relationships between utility functions and optimal spare configurations. Then we extend our branch and bound algorithm and incorporate a dynamic programming approach to develop the first framework for optimal and e-optimal (i.e., within epsilon of optimal, typically at much lower area overhead) redundancy designs for different utility functions. We demonstrate that even in an era of high defect density which leads to extremely low yield, we are able to combine approaches in a way that provide figure of merit that is up to 83.8% of that of the ideal case, i. e., for a process with zero defect density.