Reliability Evaluation of Copper (Cu) Through-Silicon Via (TSV) Barrier and Dielectric Liner by Electrical Characterization

The purpose of this study is to analyze the failure mechanisms of copper (Cu) through silicon via (TSV) with titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner, following various stress tests such as electrical, temperature cycling (TC) and high temperature storage (HTS) via electrical characterization methods. The various stresses are performed individually or in a combination of TC or HTS with electrical bias for comparison. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were plotted after the respective stresses, to detect any changes in its electrical characteristics. Results from C-V and J-E plots suggest that barrier degradation is related to material and structural influence. The degradation in the barrier layer can lead to Cu diffusion and drift into the dielectric layer, which is reflected by changes to the minimum depletion capacitance measured in the C-V curve. An increase or decrease in the minimum depletion capacitance measured indicates Cu ions presence in SiO2 or silicon (Si) substrate respectively. The individual stresses performed reveal that there was insignificant copper existence in the dielectric layer. However a combination of stresses which involves an additional electrical bias stress on TC or HTS sample better enabled the detection of degraded barrier by electrical means. The electrical bias serves as a driving force for Cu ions drift through degraded barrier as Cu does not readily diffuse into SiO2 at room temperature. On the other hand, by increasing the number of TSVs measured in an array structure, it is found that degraded barrier and Cu trace was detected without the need for subsequent electrical bias stress.