Accelerated yield learning in aggressive lithography

As exposure wavelengths decrease from 248nm to 193, 157, and even 13nm (EUV), small process defects can cause collapse of the lithographic process window near the limits of resolution, particularly for the gate and contact structures in high-performance devices. Such sensitivity poses a challenge for lithography process module control. In this work, we show that yield loss can be caused by a combination of macro, micro, CD, and overlay defects. A defect is defined as any yield-affecting process variation. Each defect, regardless of cause, is assumed to have a specific "kill potential". The accuracy of the lithographic yield model can be improved by identifying those defects with the highest kill potential or, more importantly, those that pose the highest economic risk. Such economic considerations have led us to develop a simple heuristic model for understanding sampling strategies in defect metrology and for linking metrology capability to yield and profitability.