On-chip testing of embedded silicon transducers

被引:0
作者
Mir, S [1 ]
Charlot, B [1 ]
Rufer, L [1 ]
Courtois, B [1 ]
机构
[1] TIMA Lab, F-38031 Grenoble, France
来源
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年
关键词
MEMS; failure mechanisms; defects; fault modeling; fault simulation; A-HDL; built-in self-test;
D O I
10.1109/SOCC.2004.1362334
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
System-on-Chip (SoC) technologies are evolving towards the integration of highly heterogeneous devices, including hardware of a different nature, such as digital, analog and mixed-signal, together with software components. Embedding transducers, as predicted by technology roadmaps, is yet another step in this continuous search for higher levels of integration and miniaturisation. Embedded transducers fabricated with silicon/ CMOS compatible technologies may have more limitations than transducers fabricated with fully dedicated technologies. However, they offer Industry the possibility of providing low cost applications for very large market niches, while still keeping, acceptable transducer sensitivity. This is the case, for example, for accelerometers, micro-mirrors display devices or CMOS imagers Embedded transducers are analog components. But given the fact that they work with signals other than electrical, the test of these embedded parts poses new challenges. Test technology for SoC devices is rapidly maturing but many difficulties still remains, in particular for addressing the test of analog and mixed-signal-paris. In this paper, we will present our work in the field of MEMS (Micro-Electro-Mechanical Systems) on-chip testing with a brief overview of the state-of-the-art.
引用
收藏
页码:13 / 18
页数:6
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