15-nm Channel Length MoS2 FETs with Single- and Double-Gate structures

被引:0
|
作者
Nourbakhsh, A. [1 ,2 ]
Zubair, A. [1 ]
Huang, S. [1 ]
Ling, X. [1 ]
Dresselhaus, M. S. [1 ]
Kong, J. [1 ]
De Gendt, S. [2 ,3 ]
Palacios, T. [1 ]
机构
[1] MIT, 77 Massachusetts Ave, Cambridge, MA 02139 USA
[2] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[3] KULeuven, B-3001 Leuven, Belgium
来源
2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY) | 2015年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We demonstrate single-and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (L-S/D) of 15 nm built on monolayer (t(ch)similar to 0.7 nm) and 4-layer (t(ch)similar to 3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with L-S/D=15 nm, had an I-on/I-off in excess of 10(6) and a minimum subthreshold swing (SSmin.) of 90 mV/dec. at V-DS=0.5 V. At L-S/D=1 mu m and V-DS=0.5 V, SSmin.=66 mV/dec., which is the best SS reported in MoS2 FETs, indicating the high quality of the interface and the enhanced channel electrostatics.
引用
收藏
页数:2
相关论文
共 49 条
  • [21] NDR Behavior of a Phosphorous-Doped Double-Gate MoS2 Armchair Nanoribbon Field Effect Transistor
    Durgesh Laxman Tiwari
    K. Sivasankaran
    Journal of Electronic Materials, 2020, 49 : 551 - 558
  • [22] Analog Circuits Using Double-Gate Multilayer MoS2 Field-Effect Transistor for Sensor Applications
    Vasishta, Sudhanva
    Wang, Xiao
    Rodder, Michael
    Raghunandan, K. R.
    Viswanathan, T. R.
    Dodabalapur, Ananth
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (06) : 3470 - 3476
  • [23] Low-power double-gate MoS2 negative capacitance transistors with near-zero DIBL
    Hu, Taiqi
    Cheng, Tiedong
    Lin, Yuan
    Zhang, Tianfu
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2022, 37 (11)
  • [24] Novel 10-nm Gate Length MoS2 Transistor Fabricated on Si Fin Substrate
    Pan, Yu
    Yin, Huaxiang
    Huang, Kailiang
    Zhang, Zhaohao
    Zhang, Qingzhu
    Jia, Kunpeng
    Wu, Zhenhua
    Luo, Kun
    Yu, Jiahan
    Li, Junfeng
    Wang, Wenwu
    Ye, Tianchun
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2019, 7 (01): : 483 - 488
  • [25] NDR Behavior of a Phosphorous-Doped Double-Gate MoS2 Armchair Nanoribbon Field Effect Transistor
    Tiwari, Durgesh Laxman
    Sivasankaran, K.
    JOURNAL OF ELECTRONIC MATERIALS, 2020, 49 (01) : 551 - 558
  • [26] MoS2 Field-Effect Transistor with Sub-10 nm Channel Length
    Nourbakhsh, Amirhasan
    Zubair, Ahmad
    Sajjad, Redwan N.
    Tavakkoli, Amir K. G.
    Chen, Wei
    Fang, Shiang
    Ling, Xi
    Kong, Jing
    Dresselhaus, Mildred S.
    Kaxiras, Efthimios
    Berggren, Karl K.
    Antoniadis, Dimitri
    Palacios, Tomas
    NANO LETTERS, 2016, 16 (12) : 7798 - 7806
  • [27] Physical insights into the operation of a 1-nm gate length transistor based on MoS2 with metallic carbon nanotube gate
    Perucchini, Marta
    Marin, Enrique G.
    Marian, Damiano
    Iannaccone, Giuseppe
    Fiori, Gianluca
    APPLIED PHYSICS LETTERS, 2018, 113 (18)
  • [28] Scaling of MoS2 Transistors and Inverters to Sub-10 nm Channel Length with High Performance
    Tian, Jinpeng
    Wang, Qinqin
    Huang, Xudan
    Tang, Jian
    Chu, Yanbang
    Wang, Shuopei
    Shen, Cheng
    Zhao, Yancong
    Li, Na
    Liu, Jieying
    Ji, Yiru
    Huang, Biying
    Peng, Yalin
    Yang, Rong
    Yang, Wei
    Watanabe, Kenji
    Taniguchi, Takashi
    Bai, Xuedong
    Shi, Dongxia
    Du, Luojun
    Zhang, Guangyu
    NANO LETTERS, 2023, 23 (07) : 2764 - 2770
  • [29] Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS2 Channel Transistors
    Wu, Wen-Chia
    Hung, Terry Y. T.
    Sathaiya, D. Mahaveer
    Arutchelvan, Goutham
    Hsu, Chen-Feng
    Su, Sheng-Kai
    Chou, Ang Sheng
    Chen, Edward
    Shen, Yun-Yang
    Liew, San Lin
    Hou, Vincent
    Lee, T. Y.
    Cai, Jin
    Wu, Chung-Cheng
    Wu, Jeff
    Wong, H. -S. Philip
    Cheng, Chao-Ching
    Chang, Wen-Hao
    Radu, Iuliana P.
    Chien, Chao-Hsin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (12) : 6680 - 6686
  • [30] Intrinsic Difference Between 2-D Negative-Capacitance FETs With Semiconductor-on-Insulator and Double-Gate Structures
    You, Wei-Xiang
    Su, Pin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (10) : 4196 - 4201