15-nm Channel Length MoS2 FETs with Single- and Double-Gate structures

被引：0

作者：

Nourbakhsh, A. ^{[1
,2
]}

Zubair, A. ^{[1
]}

Huang, S. ^{[1
]}

Ling, X. ^{[1
]}

Dresselhaus, M. S. ^{[1
]}

Kong, J. ^{[1
]}

De Gendt, S. ^{[2
,3
]}

Palacios, T. ^{[1
]}

机构：

[1] MIT, 77 Massachusetts Ave, Cambridge, MA 02139 USA

[2] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[3] KULeuven, B-3001 Leuven, Belgium

来源：

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We demonstrate single-and double-gated (SG & DG) field effect transistors (FETs) with a record source-drain length (L-S/D) of 15 nm built on monolayer (t(ch)similar to 0.7 nm) and 4-layer (t(ch)similar to 3 nm) MoS2 channels using monolayer graphene as the Source/Drain contacts. The best devices, corresponding to DG 4-layer MoS2-FETs with L-S/D=15 nm, had an I-on/I-off in excess of 10(6) and a minimum subthreshold swing (SSmin.) of 90 mV/dec. at V-DS=0.5 V. At L-S/D=1 mu m and V-DS=0.5 V, SSmin.=66 mV/dec., which is the best SS reported in MoS2 FETs, indicating the high quality of the interface and the enhanced channel electrostatics.

引用

页数：2

共 49 条

[1] Symmetry of Gating in Double-Gate MoS2 FETs
Rodder, Michael A.
Dodabalapur, Ananth
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (10) : 4468 - 4473
[2] Semiconductor Capacitance Penalty per Gate in Single- and Double-Gate FETs
Majumdar, Amlan
IEEE ELECTRON DEVICE LETTERS, 2014, 35 (06) : 609 - 611
[3] Sensitivity of single- and double-gate MOS architectures to residual discrete dopant distribution in the channel
Dollfus, P.
Bournel, A.
Velazquez, J. E.
JOURNAL OF COMPUTATIONAL ELECTRONICS, 2006, 5 (2-3) : 119 - 123
[4] Sensitivity of single- and double-gate MOS architectures to residual discrete dopant distribution in the channel
P. Dollfus
A. Bournel
J. E. Velázquez
Journal of Computational Electronics, 2006, 5 : 119 - 123
[5] Phenomenological Model of Gate-Dependent Kink in I-V Characteristics of MoS2 Double-Gate FETs
Rodder, Michael A.
Dodabalapur, Ananth
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 441 - 446
[6] Single- and double-gate synaptic transistor with TaOx gate insulator and IGZO channel layer
Beom, Keonwon
Yang, Paul
Park, Daehoon
Kim, Hyung Jun
Lee, Hyun Ho
Kang, Chi Jung
Yoon, Tae-Sik
NANOTECHNOLOGY, 2019, 30 (02)
[7] Design for performance improvement via structure optimization and contact engineering in MoS2 FETs with 2 nm gate length
Wang, Fei
Ma, Xiaolei
Chen, Jiezhi
APPLIED PHYSICS EXPRESS, 2023, 16 (02)
[8] Comparison of quantum correction models for ultratin oxide single- and double-gate MOS structures under the inversion conditions
Li, YM
Yu, SM
Tang, CS
Chao, TS
2003 THIRD IEEE CONFERENCE ON NANOTECHNOLOGY, VOLS ONE AND TWO, PROCEEDINGS, 2003, : 36 - 39
[9] 10 nm Nominal Channel Length MoS2 FETs with EOT 2.5 nm and 0.52 mA/μm Drain Current
Yang, L.
Lee, R. T. P.
Rao, S. S. Papa
Tsai, W.
Ye, P. D.
2015 73RD ANNUAL DEVICE RESEARCH CONFERENCE (DRC), 2015, : 237 - 238
[10] Analysis and EOT Scaling on Top- and Double-Gate 2D CVD-Grown Monolayer MoS2 FETs
Patoary, Naim Hossain
Mamun, Fahad Al
Xie, Jing
Grasser, Tibor
Sanchez Esqueda, Ivan
ADVANCED ELECTRONIC MATERIALS, 2024, 10 (11):

← 1 2 3 4 5 →