Analysis and comparative studies on impact of Transport Delay and Transforms on the performance of TD-PLL for single phase GCI under grid disturbances

Transport delay - phase-locked loop (TD-PLL) techniques have gained much attention in recent years for designing single-phase PLL for Grid-Connected Inverters (GCIs) owing to its simple implementation structure. Some earlier works are available on design guidelines for selecting appropriate parameters of TD-PLL, but, the impact of transport delay (TD) and transformation matrix (TM) on the TD-PLL under different grid disturbances have yet not been explored in the literature. In this paper, all possible combinations of TD and TM for phase detector (PD) are explored and mathematically evaluated using small-signal and phasor analyses. Synchronization capabilities of PDs under grid disturbances were evaluated in terms of parameters like initial synchronizing speed, phase, and frequency estimation. The elements of TD-PLL responsible for the phase of synchronization and performance deviation under different grid disturbances were identified. It is also mathematically shown that the T-s/4 (a quarter of a period) TD-PLL offers better immunity against grid disturbances, faster dynamics, small settling time in comparison to its 3T(s)/4 counterpart. Numerical results using MATLAB/Simulink environment as well as the experimental results obtained using dSPACE (DS1104) were presented to validate the theoretical analyses. The results were also compared with some advanced single-phase PLLs.