Leveraging On-Chip Voltage Regulators as a Countermeasure Against Side-Channel Attacks

被引:18
作者
Yu, Weize [1 ]
Uzun, Orhun Aras [1 ]
Koese, Selcuk [1 ]
机构
[1] Univ S Florida, Tampa, FL USA
来源
2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2015年
关键词
Side-channel attacks; on-chip voltage regulation; power efficiency; DC-DC CONVERTER; POWER; EFFICIENT; DESIGN;
D O I
10.1145/2744769.2744866
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Side-channel attacks have become a significant threat to the integrated circuit security. Circuit level techniques are proposed in this paper as a countermeasure against side-channel attacks. A distributed on-chip power delivery system consisting of multi-level switched capacitor (SC) voltage converters is proposed where the individual interleaved stages are turned on and turned off either based on the workload information or pseudo-randomly to scramble the power consumption profile. In the case that the changes in the workload demand do not trigger the power delivery system to turn on or off individual stages, the active stages are reshuffled with so called converter-reshuffling to insert random spikes in the power consumption profile. An entropy based metric is developed to evaluate the security-performance of the proposed converter-reshuffling technique as compared to three other existing on-chip power delivery schemes. The increase in the power trace entropy with CoRe scheme is also demonstrated with simulation results to further verify the theoretical analysis.
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页数:6
相关论文
共 22 条
[1]   Integrated regulation for energy-efficient digital circuits [J].
Alon, Elad ;
Horowitz, Mark .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (08) :1795-1807
[2]  
Ambrose J. A., 2012, RANDOMIZED INSTRUCTI, V11
[3]  
Andersen TM, 2013, APPL POWER ELECT CO, P692, DOI 10.1109/APEC.2013.6520285
[4]  
Arora M., 2012, SECURE IS AES BRUTE
[5]   A survey of design techniques for system-level dynamic power management [J].
Benini, L ;
Bogliolo, A ;
De Micheli, G .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (03) :299-316
[6]  
Cevrero A, 2011, DES AUT CON, P1014
[7]   Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic [J].
Cilio, Washington ;
Linder, Michael ;
Porter, Chris ;
Di, Jia ;
Thompson, Dale R. ;
Smith, Scott C. .
MICROELECTRONICS JOURNAL, 2013, 44 (03) :258-269
[8]  
Clavier C., 2000, DIFFERENTIAL POWER A
[9]  
Kim W, 2008, INT S HIGH PERF COMP, P115
[10]   Introduction to differential power analysis [J].
Kocher, Paul ;
Jaffe, Joshua ;
Jun, Benjamin ;
Rohatgi, Pankaj .
JOURNAL OF CRYPTOGRAPHIC ENGINEERING, 2011, 1 (01) :5-27