Common-mode backchannel signaling system for differential high-speed links

被引：14

作者：

Ho, A ^{[1
]}

Stojanovic, V ^{[1
]}

Chen, F ^{[1
]}

Werner, C ^{[1
]}

Tsang, G ^{[1
]}

Alon, E ^{[1
]}

Kollipara, R ^{[1
]}

Zerbe, J ^{[1
]}

Horowitz, MA ^{[1
]}

机构：

[1] Rambus Inc, Los Altos, CA 94022 USA

来源：

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2004年

关键词：

common-mode; backchannel; high-speed links;

D O I：

10.1109/VLSIC.2004.1346612

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell [1]. A transceiver chip was designed in 0.13mum CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a three-level return-to-null signaling scheme with simultaneous voltage and timing reference extraction, to minimize the hardware costs and achieve robust operation for sending update information from receiver to the transmitter. The measured results indicate that this backchannel achieves reliable communication without noticeable impact on the forward link for bandwidths up to 50MHz and swings of 20-100mV.

引用

页码：352 / 355

页数：4