IP Protection of Mesh NoCs Using Square Spiral Routing

被引:8
作者
Liu, Qiang [1 ]
Ji, Wenqing [1 ]
Chen, Qi [1 ]
Mak, Terrence [2 ]
机构
[1] Tianjin Univ, Sch Elect Informat Engn, Tianjin 300072, Peoples R China
[2] Univ Southampton, Dept Elect Comp Sci, Southampton SO17 1BJ, Hants, England
基金
中国国家自然科学基金;
关键词
Digital watermarks; intellectual property (IP) protection; network-on-chip (NoC); routing algorithm; WATERMARKING; SCHEME;
D O I
10.1109/TVLSI.2015.2462842
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Intellectual property (IP) core reuse is essential for the design process of system-on-chip (SoC). Network-on-chip (NoC) has been used as an independent IP core during SoC design. However, the NoC has not been protected via IP protection and paid attention on its innovations. This paper proposes the first known approach to protect the authorship and the usage legitimacy of NoCs using specially designed routing, square spiral routing. The special routing algorithm exploits routing redundancy inherent in the mesh NoCs and transports packets along the paths, which have very low probability to be taken under commonly used routing algorithms. These unique and diverse paths are exploited in this paper to embed information of the author and identify the legal buyer of NoCs, showing high robustness and credibility. The hardware implementation of an IP-protected mesh NoC shows that the area overhead is small, which is similar to 0.74%, and the power overhead is similar to 0.52%, while the functionality and performance of the network is not affected. In this paper, the approach is presented for the mesh NoC, but the idea is equally applicable to other NoC topologies where the unique and diverse paths also inherently exist.
引用
收藏
页码:1560 / 1573
页数:14
相关论文
共 27 条
[1]   A public-key watermarking technique for IP designs [J].
Abdel-Hamid, AT ;
Tahar, S ;
Aboulhamid, EM .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, :330-335
[2]   A survey on IP watermarking techniques [J].
Abdel-Hamid, AT ;
Tahar, S ;
Aboulhamid, EM .
DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2004, 9 (03) :211-227
[3]  
[Anonymous], 2001, FED INF PROC STAND P
[4]  
Bogdanov A, 2011, LECT NOTES COMPUT SC, V7073, P344, DOI 10.1007/978-3-642-25385-0_19
[5]   IPP@HDL: Efficient intellectual property protection scheme for IP cores [J].
Castillo, Encarnacion ;
Meyer-Baese, Uwe ;
Garcia, Antonio ;
Parrilla, Luis ;
Lloris, Antonio .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (05) :578-591
[6]   A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection [J].
Chang, Chip-Hong ;
Zhang, Li .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2014, 33 (01) :76-89
[7]   Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property [J].
Chang, Chip-Hong ;
Cui, Aijiao .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (07) :1618-1630
[8]   IP protection of DSP algorithms for system on chip implementation [J].
Chapman, R ;
Durrani, TS .
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2000, 48 (03) :854-861
[9]  
Cui AJ, 2011, IEEE INT SYMP CIRC S, P2333
[10]   A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design [J].
Cui, Aijiao ;
Chang, Chip-Hong ;
Tahar, Sofiene ;
Abdel-Hamid, Amr T. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2011, 30 (05) :678-690