Design methodology for a large communication chip

被引：5

作者：

Clauberg, R ^{[1
]}

Buchmann, P ^{[1
]}

Herkersdorf, A ^{[1
]}

Webb, DJ ^{[1
]}

机构：

[1] IBM Res, Zurich Res Lab, High Speed Adapters Grp, CH-8803 Ruschlikon, Switzerland

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2000年 / 17卷 / 03期

关键词：

D O I：

10.1109/54.867899

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains. It also couples a large digital design to a mixed-signal part in physical design.

引用

页码：86 / 94

页数：9

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