Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor-Transistor Hybrid FPGA Architecture

Field-programmable gate arrays (FPGAs) have come a long way from being used as glue logic to complete system solution. This is mainly because of their generalized reconfigurable nature, low non-recurring engineering (NRE) cost, and rapid time to market. However, their advantages come at the cost of larger area and higher power consumption eventually making them unsuitable for area and power critical applications. In this work, we propose a novel memristor-transistor hybrid FPGA architecture. Memristor-transistor-based building blocks of FPGA architecture are designed and simulated using HSPICE in this work. Results show that hybrid blocks on average take 30.3 % less area and consume 64.3 % less power compared to transistor-only blocks. Hybrid blocks are combined together to construct logic blocks [i.e., look-up tables (LUTs) and configurable logic blocks] and routing switches of hybrid FPGA architecture. Furthermore, a generalized exploration environment is developed to explore the effect of LUT size on the area and power consumption of memristor-transistor hybrid FPGA architecture. For experimental purpose, sixteen largest MCNC benchmarks are used and LUT size is varied from three to seven. Experimental results show that LUT-4 gives the best area and power results for memristor-transistor hybrid FPGA architecture.