A Table Look-Up Based Ternary Neural Network Processor

被引:5
作者
Suzuki, Yuta [1 ]
Soga, Naoto [1 ]
Sato, Shimpei [1 ]
Nakahara, Hiroki [1 ]
机构
[1] Tokyo Inst Technol, Tokyo, Japan
来源
2020 IEEE 50TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2020) | 2020年
关键词
Ternary DNN; Embedded System; Deep Learning;
D O I
10.1109/ISMVL49045.2020.000-7
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Matrix calculations dominate deep neural network (DNN) operations. Edge devices with applications in computer vision and embedded processors tend to be slower, and therefore, they are not suitable for real-time performance. Recently, dedicated processors have been developed, most of which have product-sum operation circuits. However, the area of the arithmetic circuit is large. In this paper, we propose an inference processor with a table look-up method. By storing the output of the DNN in a table in advance, an arithmetic circuit can be eliminated. We introduce ternary weights that can be realized with a small amount of memory and aid in reduction of zero weights. We show the training algorithm for the ternary weight DNN and the memory storage method by functional decomposition. The overall architecture for a sparse weight is described. To elucidate the superiority of ternary neural networks, we have compared binarization and ternarization. Experimental results show that ternarization reduced memory usage by 92% compared to binarization, while the recognition accuracy slightly improved. Thorough comparison also revealed that our proposed look-up based processor is 41 times faster than an Arduino embedded processor.
引用
收藏
页码:188 / 193
页数:6
相关论文
共 20 条
[1]  
Ando K, 2017, SYMP VLSI CIRCUITS, pC24, DOI 10.23919/VLSIC.2017.8008533
[2]  
[Anonymous], 2016, Bitwise Neural Networks
[3]  
[Anonymous], DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
[4]  
[Anonymous], 1992, Oct Tools Distribution, V2, P197
[5]  
B. L. Synthesis and V. Group, ABC SYST SEQ SYNTH V
[6]  
Glorot X etal, 2011, AIstats, P315
[7]  
Ha D, 2018, Deep Learning for Classical Japanese Literature
[8]  
Han S, 2015, ADV NEUR IN, V28
[9]  
Hubara I, 2018, J MACH LEARN RES, V18
[10]   Odin II - An Open-source Verilog HDL Synthesis Tool for CAD Research [J].
Jamieson, Peter ;
Kent, Kenneth B. ;
Gharibian, Farnaz ;
Shannon, Lesley .
2010 18TH IEEE ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2010), 2010, :149-156