Cycle time management during production ramp-up

被引:50
作者
Haller, M [1 ]
Peikert, A [1 ]
Thoma, J [1 ]
机构
[1] Infineon Technol AG, Dept OE PR, D-81609 Munich 81609, Germany
关键词
D O I
10.1016/S0736-5845(02)00078-9
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Aggressive capacity ramp rate of a semiconductor wafer fabrication is vital for the commercial success of the enterprise. Basic requirements are short and stable production cycle times to timely qualify equipment and to provide acceptable yield. Therefore, in the ramp-up environment which is characterized by high variability and uncertainty, an adequate methodology is required to properly manage the conflict of short cycle times and fast throughput increase. This paper presents a methodology to manage cycle time by closely monitoring and limiting the work in process (WIP), by means of the so-called "WIP caps". Used consequently, this methodology allows the ramp rate to accelerate as soon as the factory performance enables this while keeping cycle times under control. (C) 2003 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:183 / 188
页数:6
相关论文
共 3 条
[1]  
ROGER EB, 1998, LEARNING PROCESS IMP
[2]  
WALLACE JH, 1996, FACTORY PHYSICS, P125
[3]  
WALLACE JH, 1996, FACTORY PHYSICS FDN, P323