Using BIST control for pattern generation

被引：42

作者：

Kiefer, G ^{[1
]}

Wunderlich, HJ ^{[1
]}

机构：

[1] Univ Stuttgart, Comp Architecture Lab, D-70565 Stuttgart, Germany

来源：

ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY | 1997年

关键词：

deterministic BIST; scan-based BIST;

D O I：

10.1109/TEST.1997.639636

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.

引用

页码：347 / 355

页数：9