A statistical methodology for modeling and analysis of path delay faults in VLSI circuits

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has dramatically increased. Testing such circuits is becoming a severe problem. With the increased densities of integrated circuits, several different types of faults can occur. Faults in disital circuits which result from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test (Shelly, J. H. and Trayon, D. Ii., Statistical techniques of timing verification. In Proc. 20th Design Automation Conf., 1983, pp. 396-402; Tendokar, N. N., Analysis of timing failures due to random AC defects in VLSI circuits. In Proc. 22nd Design Automation Conf., 1985, pp. 709-714; Park, E. S., Mercer, M. R. and Williams, T. W., A statistical model for delay fault testing. IEEE Design and Test of Computers, 1989, February, 45-55). In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, end predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits (Hamad, M. and Landis, D., A statistical model for path delay faults in VLSI circuits;fn Proc. IEEE South East Conf., April 1996, pp. 388-392) which takes into account multiple delay faults along any signal path. We define and compute the path delay fault probabilities for all paths in a circuit; the single fault assumption is only a special case of our path delay fault model. Furthermore, we demonstrate how our statistical model is used to predict such important information as the maximum number of path delay faults in a circuit. Finally, we show that when multiple faults are considered during circuit analysis, the path delay fault probability, pp, and not the delay defect probability, p, should be used in the evaluation of system parameters such as statistical delay fault coverage, yield, ant AC quality level. (C) 1998 Elsevier Science Ltd.