High performance 0.2μm dual gate complementary MOS technologies by suppression of transient-enhanced-diffusion using rapid thermal annealing

被引:2
作者
Nishida, Y [1 ]
Sayama, H
Shimizu, S
Kuroi, T
Furukawa, A
Teramoto, A
Uchida, T
Inoue, Y
Nishimura, T
机构
[1] Mitsubishi Electr Corp, ULSI Lab, Itami, Hyogo 664, Japan
[2] Mitsubishi Electr Corp, Adv Technol R&D Ctr, Itami, Hyogo 664, Japan
来源
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 1998年 / 37卷 / 3B期
关键词
silicon; MOSFET; transient-enhanced-diffusion; rapid thermal annealing; point defect; channel engineering; dual gate CMOS;
D O I
10.1143/JJAP.37.1054
中图分类号
O59 [应用物理学];
学科分类号
摘要
Rapid thermal annealing (RTA) before the low temperature process is introduced in the 0.2 mu m dual gate complementary metal oxide semiconductor (CMOS) process and its effect has been systematically investigated. Channel profiles of boron and phosphorus remain steep by the additional RTA process before gate oxidation, as seen by using secondary ion mass spectrometry and a simulation with the point defect based diffusion model. The most effective temperature to suppress transient-enhanced-diffusion (TED) is 900-1000 degrees C, Which can be remarkably suppressed by a 30 s treatment in the case of 900 degrees C RTA. A steep channel profile decreases the threshold voltage and increases the transconductance. Shallow source/drain extension profiles of BF2 and phosphorus can be fabricated by an additional RTA process before sidewall spacer film deposition, which can improve the threshold voltage lowering. Consequently, a high current drivability of a 0.2 mu m CMOS has been achieved by the suppression of TED using two additional RTA processes.
引用
收藏
页码:1054 / 1058
页数:5
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