Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

被引:122
作者
Ferrandi, Fabrizio [1 ]
Lanzi, Pier Luca [1 ]
Pilato, Christian [1 ]
Sciuto, Donatella [1 ]
Tumeo, Antonino [1 ]
机构
[1] Politecn Milan, Dipartimento Elettron & Informaz, I-20133 Milan, Italy
关键词
Ant colony optimization (ACO); communications; field programmable gate arrays (FPGA); mapping; multiprocessors; scheduling; HARDWARE; COSYNTHESIS; OPTIMIZATION;
D O I
10.1109/TCAD.2010.2048354
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
To exploit the power of modern heterogeneous multiprocessor embedded platforms on partitioned applications, the designer usually needs to efficiently map and schedule all the tasks and the communications of the application, respecting the constraints imposed by the target architecture. Since the problem is heavily constrained, common methods used to explore such design space usually fail, obtaining low-quality solutions. In this paper, we propose an ant colony optimization (ACO) heuristic that, given a model of the target architecture and the application, efficiently executes both scheduling and mapping to optimize the application performance. We compare our approach with several other heuristics, including simulated annealing, tabu search, and genetic algorithms, on the performance to reach the optimum value and on the potential to explore the design space. We show that our approach obtains better results than other heuristics by at least 16% on average, despite an overhead in execution time. Finally, we validate the approach by scheduling and mapping a JPEG encoder on a realistic target architecture.
引用
收藏
页码:911 / 924
页数:14
相关论文
共 44 条
[1]  
[Anonymous], 2004, ANT COLONY OPTIMIZAT
[2]  
[Anonymous], LATE BREAKING PAPERS
[3]  
*ATMEL, ATMEL D940HF CHIP
[4]   Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration [J].
Banerjee, Sudarshan ;
Bozorgzadeh, Elaheh ;
Dutt, Nikil D. .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (11) :1189-1202
[5]  
BEATY SJ, 1993, P INT C ART NEUR NET, P496
[6]   ON THE COMPLEXITY OF SCHEDULING PROBLEMS FOR PARALLEL PIPELINED MACHINES [J].
BERNSTEIN, D ;
RODEH, M ;
GERTNER, I .
IEEE TRANSACTIONS ON COMPUTERS, 1989, 38 (09) :1308-1313
[7]   Resource-constrained project scheduling: Notation, classification, models, and methods [J].
Brucker, P ;
Drexl, A ;
Mohring, R ;
Neumann, K ;
Pesch, E .
EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 1999, 112 (01) :3-41
[8]  
Chang PC, 2008, DES AUT CON, P776
[9]  
Chiang CW, 2008, J INTELL FUZZY SYST, V19, P345
[10]  
Dick RP, 1998, HARDW SOFTW CODES, P97, DOI 10.1109/HSC.1998.666245