Low discharge precharge free matchline structure for energy-efficient search using CAM

Design of associative memories such as content addressable memories (CAMs) is a challenging task as the demand of high search speed and low power are given the utmost importance. CAMs are wide spread in computing devices those require a precharge phase prior to every search. It lessens the frequency of search and consumes more power. Precharge free CAM (PF-CAM) is an alternative solution in reducing the power associated with matchline due to the void of additional precharge cycle. In this paper, an energy efficient precharge free CAM (EEPF-CAM) structure is proposed to reduce the power dissipation along with extra cycle time. The proposed structure of 32 x 16-bit size has been designed using predictive 45-nm CMOS technology and post layout simulations performed in SPECTRE at the supply voltage of 1 V. The architecture consuming 4.31 mu W power dissipation, resulted in an energy competence of 0.66 fJ/bit/search. The requirement of energy of the proposed EEPF-CAM architecture is reduced by 23.43% and 85.71% compared to the existed low power precharge free (LPPF) and self-controlled precharge free (SCPF) CAMs respectively in single search. For 25 repetitive searches, an improvement of 72.73% and 92.72% in energy has been obtained compared to LPPF and SCPF CAMs. Evaluation time requirement in the proposed scheme is same as that of SCPF-CAM and is enhanced compared to LPPF-CAM.