ULPAC: A Miniaturized Ultralow-Power Atomic Clock

被引:41
作者
Zhang, Haosheng [1 ]
Herdian, Hans [1 ]
Narayanan, Aravind Tharayil [2 ]
Shirane, Atsushi [1 ]
Suzuki, Mitsuru [3 ]
Harasaka, Kazuhiro [3 ]
Adachi, Kazuhiko [3 ]
Goka, Shigeyoshi [4 ]
Yanagimachi, Shinya [5 ]
Okada, Kenichi [1 ]
机构
[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Tokyo 1528552, Japan
[2] Ericsson AB, S-22362 Lund, Sweden
[3] Ricoh Co Ltd, Natori, Miyagi 9811241, Japan
[4] Tokyo Metropolitan Univ, Dept Elect Engn & Comp Sci, Tokyo 1920397, Japan
[5] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058563, Japan
关键词
Resonant frequency; Laser stability; Atomic clocks; Circuit stability; Stability analysis; Frequency modulation; Vertical cavity surface emitting lasers; Atomic clock; CMOS; coherent population trapping (CPT); frequency stability; phase-locked loop (PLL); quantum package; quantum technologies; satellite constellations; soft-error tolerant; voltage-controlled oscillator (VCO); verticalcavity surface-emitting laser (VCSEL); PASSIVE FREQUENCY STANDARDS; SHORT-TERM STABILITY; COMB SPECTROMETER; LOCAL OSCILLATOR; INTENSITY NOISE; LINE; RESONANCES; VAPOR; CMOS; GAS;
D O I
10.1109/JSSC.2019.2941004
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article introduces a chip-scale ultralow-power atomic clock (ULPAC) in the microwave frequency region. A new suspended quantum package architecture along with a fully integrated frequency probing and locking loop implemented in CMOS technology results in a compact package and ultralow-power consumption. In addition, dedicated low-noise magnetic field and temperature control loops are incorporated for isolating and mitigating the internal and external factors affecting the frequency stability. The output frequency of a crystal oscillator is continuously compensated and stabilized by locking to the peak of a coherent population trapping signal, thereby inheriting the superior frequency stability of the atomic resonance. The proposed ULPAC system achieves a frequency stability of 2.2 x 10(-12) at an averaging time of 10(5) s, while consuming 59.9 mW. The frequency probing and locking circuits implemented in a standard 65-nm CMOS process node occupy an area of 2.55 mm(2). The prototype of this atomic clock occupies a volume of 15 cm(3).
引用
收藏
页码:3135 / 3148
页数:14
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