Quasi-3-D velocity saturation model for multiple-gate MOSFETs

被引:7
作者
Han, Jin-Woo [1 ]
Lee, Choong-Ho
Park, Donggun
Choi, Yang-Kyu
机构
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Div Elect Engn, Taejon 305701, South Korea
[2] Samsung Elect Co Ltd, Semicond Res & Dev Ctr, Yongin 449711, South Korea
关键词
characteristic length; FinFET; impact ionization; multiple-gate MOSFET; substrate current; trigate; velocity saturation;
D O I
10.1109/TED.2007.894595
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a quasi-3-D velocity saturation model for a multiple-gate MOSFET based on a calculation of Gauss's equation. A new and compact velocity saturation region length is derived from a simple approximation of the electric field distribution in the pinchoff region. It is found that the length of the velocity saturation region increases with the increment of gate length and fin width. This new model is used to derive an analytical expression of a substrate current for a trigate MOSFET. In order to improve the accuracy of the substrate current model, the newly derived substrate current model introduces a parasitic potential drop across a thin-extension region and a dimensionless fitting parameter. A body-tied trigate MOSFET is fabricated on a bulk wafer so that the substrate current could be measured by its body contact. The new substrate current model is then compared with measurement data for a trigate MOSFET, and good agreement is observed.
引用
收藏
页码:1165 / 1170
页数:6
相关论文
共 14 条
[1]  
[Anonymous], VLSI S
[2]   MOSFET SUBSTRATE CURRENT MODEL FOR CIRCUIT SIMULATION [J].
ARORA, ND ;
SHARMA, MS .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1991, 38 (06) :1392-1398
[3]   A SIMPLE METHOD TO CHARACTERIZE SUBSTRATE CURRENT IN MOSFETS [J].
CHAN, TY ;
KO, PK ;
HU, C .
IEEE ELECTRON DEVICE LETTERS, 1984, 5 (12) :505-507
[4]  
Choi Y. K., 2001, IEDM, P421
[5]  
Choi YK, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P177
[6]   Analysis of the parasitic S/D resistance in multiple-gate FETs [J].
Dixit, A ;
Kottantharayil, A ;
Collaert, N ;
Goodwin, M ;
Jurezak, M ;
De Meyer, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (06) :1132-1140
[7]   High performance fully-depleted tri-gate CMOS transistors [J].
Doyle, BS ;
Datta, S ;
Doczy, M ;
Hareland, S ;
Jin, B ;
Kavalieros, J ;
Linton, T ;
Murthy, A ;
Rios, R ;
Chau, R .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (04) :263-265
[8]   A new substrate current model for submicron MOSFET's [J].
Kolhatkar, JS ;
Dutta, AK .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (04) :861-863
[9]   FinFET design considerations based on 3-D simulation and analytical modeling [J].
Pei, G ;
Kedzierski, J ;
Oldiges, P ;
Ieong, M ;
Kan, ECC .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (08) :1411-1419
[10]   EFFECTS OF THE VELOCITY SATURATED REGION ON MOSFET CHARACTERISTICS [J].
TAKEUCHI, K ;
FUKUMA, M .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (09) :1623-1627