A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs

被引：0

作者：

Luo, Pei-Wen ^{[1
]}

Chen, Chi-Kang ^{[1
]}

Sung, Yu-Hui ^{[2
]}

Wu, Wei ^{[3
]}

Shih, Hsiu-Chuan ^{[1
]}

Lee, Chia-Hsin ^{[1
]}

Lee, Kuo-Hua ^{[2
]}

Lie, Ming-Wei ^{[2
]}

Lung, Mei-Chiang ^{[2
]}

Lu, Chun-Nan ^{[2
]}

Chou, Yung-Fa ^{[1
]}

Shih, Po-Lin ^{[2
]}

Kee, Chung-Hu ^{[2
]}

Shiah, Chun ^{[2
]}

Stolt, Patrick ^{[3
]}

Tomishima, Shigeki ^{[3
]}

Kwai, Ding-Ming ^{[1
]}

Rong, Bor-Doou ^{[2
]}

Lu, Nicky ^{[2
]}

Lu, Shih-Lien ^{[3
]}

Wu, Cheng-Wen ^{[1
]}

机构：

[1] ITRI, Hsinchu, Taiwan

[2] Etron Technol, Hsinchu, Taiwan

[3] Intel Corp, Hillsboro, OR 97124 USA

来源：

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and <10ns read latency on a 45nm DRAM process. The architecture is based on small subarrays with short WL and BL to realize the low latency and energy efficiency. We also integrated several circuit techniques, including adaptive power to speed-up access time and banks rotation to reduce thermal issues. The proposed device is also estimated in a system simulation that shows that the power efficiency is higher than comparable systems.

引用

页数：2

共 1 条

[1] A 1.2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV
Lee, Dong Uk
Kim, Kyung Whan
Kim, Kwan Weon
Kim, Hongjung
Kim, Ju Young
Park, Young Jun
Kim, Jae Hwan
Kim, Dae Suk
Park, Heat Bit
Shin, Jin Wook
Cho, Jang Hwan
Kwon, Ki Hun
Kim, Min Jeong
Lee, Jaejin
Park, Kun Woo
Chung, Byongtae
Hong, Sungjoo
2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 432 - +

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