Performance Trade-offs in FinFET and Gate-All Around Device Architectures for 7nm-node and Beyond

被引：0

作者：

Kim, Seong-Dong ^{[1
]}

Guillorn, Michael ^{[2
]}

Lauer, Isaac ^{[2
]}

Oldiges, Phil ^{[1
]}

Hook, Terence ^{[3
]}

Na, Myung-Hee ^{[1
]}

机构：

[1] IBM Res, Hopewell Jct, NY 12533 USA

[2] IBM Res, Yorktown Hts, NY 10598 USA

[3] IBM Res, Essex Jct, VT 05452 USA

来源：

2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2015年

关键词：

FinFET; gate-all-around (GAA); Nanowire (NW); Nanosheet (NS); TCAD;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

A comparative DC and AC performance evaluation between tri-gate FinFETs and gate-all-around nanowire FETs is carried out for potential sub-7nm technology node. The comparative analysis of the intrinsic and parasitic components using the classical drift-diffusion transport and quantization models indicates that a wider and thinner stacked nanosheet-type design can address the issues associated with conventional nanowire devices while demonstrating improved performance relative to FinFET. The optimization of the wire suspension region is found to be critical for I-eff-C-eff performance trade-offs.

引用

页数：3

共 10 条

[1] Performance Trade-offs in Complementary FET (CFET) Device Architectures for 3nm-node and Beyond
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