Unified process-aware system for circuit layout verification

One of the challenges in establishing quantitative manufacturability metrics has been establishing a single design quality metric able to describe how a given region in the layout would perform under a specific manufacturing process. Historically, critical area analysis has been sufficient to evaluate the possible yield of a design, but as the relative importance of systematic mechanisms increases, this purely statistical approach needs to be enhanced by incorporating additional process information. In this paper we describe a consolidated metric and the system that can analyze multiple process conditions and different configurations to arrive to an optimal solution. This solution is based on a cost function which depends on the characteristics of the manufacturing process. A general form of the cost function and the parameters defining individual process impacts are discussed and, to demonstrate the system, different layout configurations are analyzed taking into account lithography process variations, random defect distributions, and recommended design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically determine the most robust layout implementation according to the cost function that incorporates the current relative importance of each yield loss contributor.