Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

被引：18

作者：

Daamen, R. ^{[1
]}

Bancken, P. H. L. ^{[1
]}

Badaroglu, D. Emur ^{[1
]}

Michelon, J. ^{[1
]}

Nguyen, V. H. ^{[1
]}

Verhden, G. J. A. M. ^{[1
]}

Humbert, A. ^{[1
]}

Waeterloos, J. ^{[2
]}

Yang, A. ^{[3
]}

Cheng, J. K. ^{[3
]}

Chen, L. ^{[3
]}

Martens, T. ^{[3
]}

Hoofman, R. J. O. M. ^{[1
]}

机构：

[1] NXP Semicond Res, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Dow Chem Co USA, Edegem, Belgium

[3] NXP Semicond, IMO Backend Innovat, Kaohsiung, Taiwan

来源：

PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2007年

关键词：

D O I：

10.1109/IITC.2007.382349

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

In this work, we propose and verify a robust dual damascene air gap architecture, which avoids the increasing complexity and cost normally associated with current multilevel air gap integration. Air gap packaging reliability was also addressed showing promising stud bonding and wire pull test results. Furthermore two solutions are proposed to solve any possible un-landed via issues, including simultaneous air gap formation at multiple metal levels, which could even be used to reduce the thermal budget for the 32/22nm nodes.

引用

页码：61 / +

页数：2

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