Low-voltage swing logic circuits for a pentium® 4 processor integer core

被引：11

作者：

Deleganes, DJ ^{[1
]}

Barany, M ^{[1
]}

Geannopoulos, G ^{[1
]}

Kreitzer, K ^{[1
]}

Morrise, M ^{[1
]}

Milliron, D ^{[1
]}

Singh, AP ^{[1
]}

Wijeratne, S ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97123 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 01期

关键词：

adders; integrated circuit design; microprocessors;

D O I：

10.1109/JSSC.2004.838020

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Pentium(R) 4 processor architecture uses a 2x frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

引用

页码：36 / 43

页数：8

共 8 条

[1]

DELEGANES D, 2004, INTEL TECHNOL J FEB

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2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :154-155

[3]

MORRISE M, 2003, Patent No. 6557149

[4]

SAGER D, 2001, ISSCC, P324

[5]

Sakurai T, 1997, 1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS, P1, DOI 10.1109/LPE.1997.621198

[6] A scalable X86 CPU design for 90nm process [J].

Schutz, J ;

Webb, C .

2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 :62-63

[7] A mixed signal rotator/shifter for 8GHz Intel® Pentium® 4 Integer Core [J].

Singh, AP ;

Barany, M ;

Deleganes, DJ .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :394-397

[8]

Thompson S, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P61, DOI 10.1109/IEDM.2002.1175779

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