A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging

被引：46

作者：

Radke, RE ^{[1
]}

Eshraghi, A

Fiez, TS

机构：

[1] LSI Log, Mixed Signal Design Ctr, Ft Collins, CO 80525 USA

[2] IBM Corp, Wireless Commun Design Ctr, Waltham, MA 02451 USA

[3] Oregon State Univ, Dept Elect & Comp Engn, Corvallis, OR 97330 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 08期

基金：

美国国家科学基金会;

关键词：

data converter; dynamic element matching;

D O I：

10.1109/4.859496

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order Sigma Delta digital-to-analog converter (DAC) with 64 x oversampling and a conversion bandwidth of 25 kHz, The systematic and random errors are considered in the design of the 14-bit converter. The Sigma Delta DAC is fabricated in a 2-mu m CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA, The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA.

引用

页码：1074 / 1084

页数：11

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