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- [1] Bounded Model Checking of Synchronous Reactive Models in Ptolemy II 2022 29TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE, APSEC, 2022, : 407 - 416
- [3] Memory models for the formal verification of assembler code using bounded model checking SEVENTH IEEE INTERNATIONAL SYMPOSIUM ON OBJECT-ORIENTED REAL-TIME DISTRIBUTED COMPUTING, PROCEEDINGS, 2004, : 129 - 135
- [5] Formal Verification of Software Designs in Hierarchical State Transition Matrix with SMT-based Bounded Model Checking 2011 18TH ASIA-PACIFIC SOFTWARE ENGINEERING CONFERENCE (APSEC 2011), 2011, : 81 - 88
- [6] Formal Verification of Ptolemy Discrete Event Model Wang, Rui (rwang04@cnu.edu.cn), 1830, Chinese Academy of Sciences (32): : 1830 - 1848
- [8] Formal verification using bounded model checking: SAT versus sequential ATPG engines 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 243 - 248
- [9] On Applying Model Checking in Formal Verification 2022 FORMAL METHODS IN COMPUTER-AIDED DESIGN, FMCAD, 2022, 3 : 3 - 3
- [10] A Formal Representation of Discrete Event Models in Ptolemy II 12TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY: ICT FOR GREEN GROWTH AND SUSTAINABLE DEVELOPMENT, VOLS 1 AND 2, 2010, : 864 - 869