Low power multiplier with bypassing and tree strucuture

被引：0

作者：

Kuo, Ko-Chi ^{[1
]}

Chou, Chi-Wen ^{[1
]}

机构：

[1] Natl Sun Yat Sen Univ, Dept Comp Sci & Engn, Kaohsiung 80424, Taiwan

来源：

2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS | 2006年

关键词：

multiplier; bypassing method; tree structure; low power;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new design technique for low power multiplier is introduced. This technique utilizes the bypassing method to minimize the switching activities and tree structure decrease the critical path. The design of circuit uses the standard TSMC 0.18 mu m technology. According to the simulation results, the proposed multiplier design can obtain more power savings than those of counterparts and achieve smaller power-delay product.

引用

页码：602 / +

页数：2

共 6 条

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[4]

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[5]

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[6]

Sangjin Hong, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454), P286, DOI 10.1109/ASIC.1999.806521

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