Application of Semi-tensor Product-based Bi-decomposition to FPGA Mapping

This paper presents a new semi-tensor product-based bi-decomposition algorithm for field programmable logic gate (FPGA) mapping with t-input look-up tables (LUTs). First, we introduce the structure matrix of a Boolean function through the technology of the semi-tensor product. Then, we break the Boolean function into smaller parts with t or less t inputs through multiple bi-decomposition of the structure matrix regardless of the specific forms of the Boolean function. The FPGA mapping is completed until all these smaller functions are replaced by t-input LUTs. Finally, we apply the proposed algorithm to a nine-input combinational logic circuit. The experimental results show the validation of the proposed algorithm. Application of Semi-tensor Product-based Bi-decomposition to FPGA Mapping.